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 HCTS245T
Data Sheet July 1999 File Number
4619.1
Radiation Hardened Octal Bus Transceiver, Three-State, Non-Inverting
Intersil's Satellite Applications FlowTM (SAF) devices are fully tested and guaranteed to 100kRAD total dose. These QML Class T devices are processed to a standard flow intended to meet the cost and shorter lead-time needs of large volume satellite manufacturers, while maintaining a high level of reliability. The Intersil HCTS245T is a Radiation Hardened NonInverting Octal Bidirectional Bus Transceiver, Three-State, intended for two-way asynchronous communication between data busses. The HCTS245T allows data transmission from the A bus to the B bus or from the B bus to the A bus. The logic level at the direction input (DIR) determines the data direction. The output enable input (OE) puts the I/O port in the high-impedance state when high.
Features
* QML Class T, Per MIL-PRF-38535 * Radiation Performance - Gamma Dose () 1 x 105 RAD(Si) - Latch-Up Free Under Any Conditions - SEP Effective LET No Upsets: >100 MEV-cm2/mg - Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day (Typ) * 3 Micron Radiation Hardened CMOS SOS * Fanout (Over Temperature Range) - Bus Driver Outputs - 15 LSTTL Loads * Significant Power Reduction Compared to LSTTL ICs * DC Operating Voltage Range: 4.5V to 5.5V * LSTTL Input Compatibility - VIL = 0.8V Max - VIH = VCC/2 Min * Input Current Levels Ii 5mA at VOL, VOH
Specifications
Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed below must be used when ordering. Detailed Electrical Specifications for the HCTS245T are contained in SMD 5962-95745. A "hot-link" is provided from our website for downloading. www.intersil.com/spacedefense/newsafclasst.asp Intersil's Quality Management Plan (QM Plan), listing all Class T screening operations, is also available on our website. www.intersil.com/quality/manuals.asp
Pinouts
HCTS245DTR (SBDIP), CDIP2-T20 TOP VIEW
DIR A0 A1 A2 A3 A4 1 2 3 4 5 6 7 8 9 20 VCC 19 OE 18 B0 17 B1 16 B2 15 B3 14 B4 13 B5 12 B6 11 B7
Ordering Information
ORDERING NUMBER 5962R9574501TRC 5962R9574501TXC PART NUMBER HCTS245DTR HCTS245KTR TEMP. RANGE (oC) -55 to 125 -55 to 125
A5 A6 A7
GND 10
HCTS245KTR (FLATPACK), CDFP4-F20 TOP VIEW
DIR A0 A1 A2 A3 A4 A5 A6 A7 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC OE B0 B1 B2 B3 B4 B5 B6 B7
NOTE: Minimum order quantity for -T is 150 units through distribution, or 450 units direct.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999 Satellite Applications FlowTM (SAF) is a trademark of Intersil Corporation.
HCTS245T Functional Diagram
ONE OF 8 TRANSCEIVERS P N P B DATA 11 (18, 17, 16, 15, 14, 13, 12) N TO OTHER 7 CIRCUITS 9 (2, 3, 4, 5, 6, 7, 8)
A DATA
DIR 1 OUTPUT ENABLE 19
TRUTH TABLE CONTROL INPUTS OE L L H DIR L H X OPERATION B Data to A Bus A Data to B Bus Isolation
H = High Voltage Level, L = Low Voltage Level, X = Immaterial To prevent excess currents in the High-Z (Isolation) modes, all I/O terminals should be terminated with 10k to 1M resistors.
2
HCTS245T Die Characteristics
DIE DIMENSIONS: (3149m x 2794m x 533m 51m) 124 x 110 x 21mils 2mil METALLIZATION: Type: Al Si Thickness: 11.0kA 1kA SUBSTRATE POTENTIAL: Unbiased Silicon on Sapphire BACKSIDE FINISH: Sapphire PASSIVATION: Type: Silox (SiO2) Thickness: 13kA 2.6kA WORST CASE CURRENT DENSITY: < 2.0e5 A/cm2 TRANSISTOR COUNT: 274 PROCESS: CMOS SOS
Metallization Mask Layout
HCTS245T
(20) VCC (19) OE (1) DIR
NC
NC
NC
A0 (2)
NC
(18) B0 A1 (3) (17) B1
A2 (4)
(16) B2
A3 (5) (15) B3
A4 (6)
(14) B4
A5 (7)
(13) B5
B7 (11)
NOTE: The die diagram is a generic plot from a similar HCS device. It is intended to indicate approximate die size and bond pad location. The mask series for the HCTS245 is TA14417A.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
3
GND (10)
B6 (12)
A6 (8)
A7 (9)


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